Authors: R. Braojos, D. Atienza

Abstract

Healthcare delivery is evolving thanks to the utilization of new Wireless Body Sensor Nodes (WBSN), which are miniaturized devices able to acquire, process and transmit subjects’ bio-signals in real time within a tiny energy budget. Recent efforts on A/D converters and transmission schemes have enabled a major power consumption reduction of these components, thus leaving the embedded processing stage as the dominant power hungry component.

In this context, new multi-core architectures designed with smaller CMOS devices and aggressive voltage scaling greatly improve the energy efficiency of WBSNs, but originate reliability operation concerns. In this work we present a novel WBSN architecture equipped with a completely re-designed memory subsystem (including a low-voltage low-latency non-volatile partition), which operates in combination with an advanced code synchronization management to reduce the platform power consumption by up to 82%.