Authors: G. Gillani, L. Oudshoorn, A.B.J. Kokkeler

Abstract

While modern energy efficient low-voltage designs focus on near-threshold voltage (NTV) operation for general purpose computing and exploiting an applications’ intrinsic error resilience by deploying PCMOS circuits for application specific computing, our results emphasize the impact of delay in PCMOS circuits at NTV and lower voltage operations. We simulated an inverter and a 4-bit ripple carry adder in Cadence that showed the shortcomings of current analytical models for probability of correctness at NTV and lower voltage supplies. We further investigated the impact of delay propagation in a digital system composed of probabilistic building blocks, which provides a clear insight of timing delay affecting the higher significant computational bits more than its lower significant counterparts and hence contributing considerably to the total error.